SOC Full Chip Verification Engineer
ID: Soc\-Ver
Description
Role Overview
Seynamics is seeking a SOC Full Chip Verification Engineer for our AI SOCs. You will develop verification infrastructure and verify end\-to\-end scenarios including CPUs, high\-speed interfaces and peripherals. We are looking for a hands\-on individual contributor with a proven track record in verification \- including testbenches, VIPs, verification test sequences, cover application scenarios \- to ensure the highest quality before tapeout.
Key Responsibilities
SOC Full Chip Verification Infrastructure* Define and establish the verification infrastructure, environment.
- Develop and implement generic testbenches for Chiplet to Chiplet Verification, Package to Package Verification.
- Models, VIPs for high\-speed interfaces and peripherals.
- Own and run CI, sanity, full regression cycles for verification.
- Functional Verification and Performance Verification.
Work at one of Europe’s most promising deep\-tech semiconductor start up \- from silicon to systems \- Se* ynamics.
- Accelerated development path.
- 4 days per week in the Barcelona office (city center), 1 day WFH.
- 1 week of work from everywhere in the world.
- Competitive package.
- A collaborative, technical, and growth\-oriented environment that values direct ownership and clear thinking.
Requirements
Must\-Have* In\-depth expertise of industry verification C ELF/ SV/ UVM methods with experience in CPUs, Cache Coherency, PCIe, AXI, CHI, Ethernet, Memory protocols.
- Minimum 6\+ years experience having signed\-off on verification for multiple projects.
- University degree in Electrical or Computer Engineering.
SENIOR
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