Design Verification Engineer SoC

*About Fondazione Chips\-IT*

*The Foundation “Italian Center for the Design of Semiconductor Integrated Circuits,” also known as the Chips\-IT Foundation, is a nonprofit research and technology organization under the supervision of the Ministries of Industry.*

*The Foundation is Italy's first RTO (Research and Technology Organization) vertically focused on semiconductor research and stands as a center of excellence in frontier research on semiconductor design, as well as a pivotal center of the Italian semiconductor ecosystem and expertise.*

*Missions of the Foundation:*

• Promote the design and development of integrated circuits


• Strengthen the system of professional training in the field of microelectronics


• Ensure the establishment of a network of universities, research centers and enterprises that fosters innovation and technology transfer in the field

The Chips\-IT Foundation is seeking an experienced Verification Engineer to support the development and validation of advanced digital IPs and System\-on\-Chip (SoC) platforms. The role focuses on creating and maintaining verification environments using industry\-standard methodologies (e.g., UVM), ensuring functional correctness of designs from specification to tape\-out. The position also involves collaboration with design, architecture, and software teams to deliver reliable and high\-quality silicon. The work can be carried out either in Pavia or in Bologna.

KEY RESPONSIBILITIES:

• Define and implement verification strategies at IP and SoC levels.


• Develop and maintain UVM\-based verification environments, including testbenches and functional coverage.


• Design and execute test plans aligned with design specifications and requirements.


• Debug RTL and simulation issues using advanced tools and techniques.


• Integrate verification components and ensure complete test coverage.


• Contribute to regression infrastructure and manage automated test execution.


• Collaborate closely with RTL designers, DFT engineers, and physical implementation teams.


• Support post\-silicon bring\-up and validation activities as needed.

• Master’s degree in Electrical Engineering, Computer Engineering, or a related field.


• At least 5 years of experience in digital design verification.


• Strong knowledge of SystemVerilog and UVM methodology.


• Hands\-on experience with simulation and debug tools (e.g., QuestaSim, VCS, Verdi).


• Familiarity with industry\-standard protocols such as AMBA AXI, APB, and AHB.


• Experience in writing constrained\-random testbenches and analyzing coverage metrics.


• Good understanding of digital design, SoC architecture, and RTL development.


• Strong teamwork, communication, and documentation skills.

WHAT WE OFFER

• Competitive compensation and contract type, to be negotiated based on qualifications and experience


• Possibility to enter into a PhD conjugating your job with a research program that will grant you the PhD title.


• Lunch tickets


• Private health care coverage depending on your role and contract


• Structured growth path, with ongoing access to training and updates


• Networking opportunities with industry\-leading professionals


• International environment


• Hybrid work policy


• Tax deductions: Candidates from abroad, comprising Italian citizens, who have carried scientific research activity abroad and meet specific requirements, may be entitled to a taxable income deduction up to 90% for a period of 6 to 13 years

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