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via Greenhouse · 8 September 2026 ·11 days ago

2027 Internship/Graduate - FPGA Engineering

quberesearchandtechnologies

London

This listing is from Greenhouse

View original listing ↗

2027 – Internship or Graduate, FPGA Engineering 
Programmes offered: Final-year internship, penultimate-year internship, some permanent opportunities 
Location: London
Programme duration: 3–6 months, or full-time graduate, starting in 2027 
Who qualifies: Penultimate or final-year students completing a bachelor’s or master’s degree 
Qube Research & Technologies (QRT) is a global quantitative and systematic investment manager operating across liquid asset classes and markets worldwide. Our approach to investing is scientific: we bring together data, research, technology and trading expertise to develop and run systematic strategies. 
Technology is central to how QRT works. Over the years, we have built a global research and execution platform spanning geographies, asset classes and trading horizons, from ultra-low-latency systems to large-scale research, analytics and risk infrastructure. We invest heavily in engineering, automation and scalable systems because better technology allows us to test ideas faster, operate more reliably and tackle harder problems. 
Our internships are designed to give students meaningful experience of that work. You’ll join a team, contribute to real projects and learn from engineers, researchers and traders working on live problems. The environment is technical, collaborative and demanding, with plenty of scope to ask questions, test ideas and take ownership. Strong performance during the internship may lead to consideration for a full-time graduate role. 
Your future role at QRT 
Throughout the recruitment process, we’ll consider your skills and interests alongside the problems our teams are working on, with the aim of finding the strongest fit. 
QRT’s FPGA team builds ultra-low-latency hardware for our trading systems. By implementing custom logic directly on FPGA devices, the team can process market data and execute orders with tight control over latency, throughput and system behaviour. 
The work sits at the boundary between hardware and software. We use SystemVerilog, C++ and Python to design, verify and integrate FPGA systems into our wider trading infrastructure. The problems are technically demanding: small design decisions can have measurable consequences, and performance needs to come with reliability. 
As an intern or graduate in the FPGA team, you will: 
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="20" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1">Build production FPGA systems – Contribute to the design, development and optimisation of FPGA-based platforms used in live trading. </li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="20" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="2" data-aria-level="1">Work across hardware and software – Use SystemVerilog, C++ and Python to build, test and refine high-performance, low-latency systems. </li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="20" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="3" data-aria-level="1">Develop and verify new functionality – Implement FPGA features that improve how our systems process market data and execute orders, and build the tests needed to verify them. </li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="20" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="4" data-aria-level="1">Integrate systems – Work with hardware and software engineers to connect FPGA components with QRT’s broader trading infrastructure. </li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="20" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="5" data-aria-level="1">Analyse performance – Debug and profile designs, investigating latency, resource utilisation and other constraints to understand where improvements can be made. </li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="20" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="6" data-aria-level="1">Work with modern FPGA technology – Gain hands-on experience with FPGA hardware, development tools and verification workflows used in low-latency trading. </li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="20" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="7" data-aria-level="1">Explore new approaches – Contribute to research and development aimed at improving the performance and capabilities of our FPGA systems. </li>
</ul>
Your present skillset 
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="18" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1">Interest in technology: You enjoy understanding how systems work and have explored that interest through software or hardware projects, whether academic, personal or hobby-based. Formal Computer Science training is not essential. </li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="18" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="2" data-aria-level="1">HDL experience: Experience or coursework using an HDL such as SystemVerilog, Verilog or VHDL. </li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="18" data-list-defn-props="{"335552541":1,"33555

This listing is from Greenhouse. View original listing ↗

2027 Internship/Graduate - FPGA Engineering

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